*Preface: VCD(Value Change Dump), VCD has nothing to do with DVD. It is a waveform storage file generated by EDA simulation software during IC design simulation. The following code*
$date Wed Oct 20 15:04:11 2021 $end $version libsigrok 0.5.2 $end $comment Acquisition with 16/16 channels at 200 MHz $end $timescale 1 ns $end $scope module libsigrok $end $var wire 3 $1 BS [2:0] $end $var wire 1 ! 0 $end $var wire 1 " 1 $end $var wire 1 # 2 $end $var wire 1 $ 3 $end $var wire 1 % 4 $end $var wire 1 & 5 $end $var wire 1 ' 6 $end $var wire 1 ( 7 $end $var wire 1 ) 8 $end $var wire 1 * 9 $end $var wire 1 + 10 $end $var wire 1 , 11 $end $var wire 1 - 12 $end $var wire 1 . 13 $end $var wire 1 / 14 $end $var wire 1 0 15 $end $upscope $end $enddefinitions $end #0 1! 1" 1# 0$ 0% 1& 1' 0( 0) 0* 0+ 0, 0- 0. 0/ 00 #2499371545 0' #2499372810 0# b000 $1 #2499998855 0! #2500004690 1$ #2500009360 0" 0$ #2500014030 1$ #2500018695 1" #2500018700 0$ #2500023370 1$ #2500028040 0" 0$ #2500032710 1$ #2500037380 0$ #2500042045 1$ #2500046715 1" 0$ #2500051380 1$ #2500056050 0" 0$ #2500060720 1$ #2500065385 1" #2500065390 0$
Inside the code block is an excerpt from the vcd document. There are several ways to produce vcd. You can judge from the information behind $version. 1. libsigrok 0.5.2 is a vcd that is captured by the logic analyzer and output through the supporting software. 2. ModelSim Version 6.6 is a vcd output through modelsim software simulation. 3，Synopsys VCS version N-2017.12-SP2_Full64 is the vcd document output by Synopsys' VCs software. The format of vcd documents output by different software is slightly different.
The VCD document as a whole contains three parts. header section ， variable definition section，value change section.
The VCD keyword starts with $(but variable identifiers can also start with $). Typically, each keyword ends with a $end keyword.
header section
$date Wed Oct 20 15:04:11 2021 $end $version libsigrok 0.5.2 $end $comment Acquisition with 16/16 channels at 200 MHz $end $timescale 1 ns $end $scope module libsigrok $end
The header section will record the file simulation date and simulation information, as well as the time accuracy during simulation.
$date: VCD is the generation time
$version: version information of simulation software.
$comment: comment instruction. Here is the sampling rate when the logic analyzer is inserted.
$timescale: the time precision used by software simulation to generate VCD.
variable definition section
$scope module libsigrok $end $var wire 3 $1 BS [2:0] $end $var wire 1 ! 0 $end $var wire 1 " 1 $end $var wire 1 # 2 $end $var wire 1 $ 3 $end $var wire 1 % 4 $end $var wire 1 & 5 $end $var wire 1 ' 6 $end $var wire 1 ( 7 $end $var wire 1 ) 8 $end $var wire 1 * 9 $end $var wire 1 + 10 $end $var wire 1 , 11 $end $var wire 1 - 12 $end $var wire 1 . 13 $end $var wire 1 / 14 $end $var wire 1 0 15 $end $upscope $end $enddefinitions $end
$scope: indicates the scope of the recorded variable.
$var: indicates the correspondence between the current identifier and the information name Here is the definition, the bit width of the signal, the identifier, and the corresponding signal name. Because it is the type captured by the logic analyzer. All signals are marked with channel numbers 0 - 15. No signal name. $var wire 1 7 D0P $end $var wire 1 8 D0N $end generated by VCS.
$upscope: indicates a change in the design hierarchy
$enddefinitions: identifies the end of header information area and node information area.
value change section:
#0 1! 1" 1# 0$ 0% 1& 1' 0( 0) 0* 0+ 0, 0- 0. 0/ 00 #2499371545 0' #2499372810 0# b000 $1 #2499998855 0! #2500004690 1$ #2500009360 0" 0$ #2500014030 1$ #2500018695 1" #2500018700 0$ #2500023370 1$ #2500028040 0" 0$ #2500032710 1$ #2500037380 0$ #2500042045 1$ #2500046715 1" 0$ #2500051380 1$ #2500056050 0" 0$ #2500060720 1$ #2500065385 1" #2500065390 0$
Values that change in chronological order are recorded in the vcd document.
#Indicates the time of change. 0 or 1 indicates the value of the signal change. Followed by the identifier of the signal. Indicates that the signal has changed# 0 means at time 0, followed by the initialization value of 0-15 signal channel# 2499371545 0 'indicates that the logic of signal 6 changes from 1 to 0 at 2499371545nS.
For vector (multi bit) signals, the format is the signal b000 $1 represented by the letter 'B' or 'B'