Daily records (84) check digit, regularity, etc.

UART serial port check mode (no check, parity check, fixed check)

concept

https://www.codenong.com/cs106550351/

  • Odd parity (ODD): Add parity bits so that the number of bits that are 1 in the entire process of each byte transmission is an odd number.
  • Even parity (EVEN): Add a parity bit so that the number of bits that are 1 in the entire process of each byte transmission is an even number.
  • No check (NONE): No check digit.
  • Fixed check digit (Stick): The check digit is the inversion of bit4 of LCR. (Set to 1 for odd parity, 0 for even parity)

Check calculation

For even parity, first take parity_bit = 0, and then add bitwise XOR to obtain even parity.
Here the check output is 1.

// even parity
module taa ();
    logic [7:0] data = 8'bxx001110;
    logic parity_bit = 0;

    initial begin
        for (int i = 0; i < 6; i++) begin
            parity_bit ^= data[i];
        end
        $display("parity bit is %0b", parity_bit);
        parity_bit = ^data[5:0];
        $display("parity bit is %0b", parity_bit);

    end
endmodule

Ctrlp plug-in to open the form of the file, shortcut keys

  • t new tab
  • v Vertical
  • h level

regular expression match

Chapter 8 Section 3

http://web.suda.edu.cn/hejun/

Detailed table

http://web.suda.edu.cn/hejun/chapter8/regular_expression_table.html

match specific

vim remove whitespace at end of line

Volatile bit understanding of UVM reg_field

When the software implements the hardware driver and firmware layer, a method similar to the mirror value of the register model will also be implemented, that is, in the underlying function of the register configuration,
It also declares some global shadow register s. The function of these shadow registers is to temporarily store the value written to the register at that time.
In later use, if these registers are non-volatile, the step of reading the registers can be omitted, and the value of the shadow register can be used instead.
The advantage of doing this is that the response is faster, and it is no longer initiated and responded through the bus of several clock cycles, but on the other hand, the premise of doing this is the same as our purpose of testing the register model.
That is, the written value of the register can be accurately reflected on the register in the hardware.
https://blog.eetop.cn/blog-1561828-6266225.html

m_volatile, volatile flag bit, in the field, when this bit is 1, it means that 1 will be returned every time needs_update is called,
That is, every time the user check s whether the register needs to be updated, the return of the field needs to be updated.
https://blog.eetop.cn/blog-1765812-6945802.html

VIM keymap problem

There are many keys in Vim that cannot be map ped, mostly because the terminal does not support such key combinations.
Link: https://www.zhihu.com/question/23225258/answer/24012145

[ctrl+v+i] can force the input tab

ctags operation

ctags --list-languages
Which languages ​​are recognized
ctags --list-maps
Which extensions correspond to which languages ​​by default
--langmap=SystemVerilog:.sv.v.svh.tv.vg.vinc
Set the extension corresponding to the language
ctags --list-kinds
See the syntax elements recognized by ctags

SystemVerilog's ctags example

--langdef=systemverilog
--langmap=systemverilog:.sv.svh.svi
--regex-systemverilog=/^[ \t]*(virtual)?[ \t]*class[ \t]*([a-zA-Z_0-9]+)/\2/c,class/

--regex-systemverilog=/^[ \t]*(virtual)?[ \t]*task[ \t]*.*::([a-zA-Z_0-9]+)[\t]*[(;]/\2/t,task/
--regex-systemverilog=/^[ \t]*(virtual)?[ \t]*function[ \t]*.*::([a-zA-Z_0-9]+)[ \t]*[(;]/\2/f,function/

--regex-systemverilog=/^[ \t]*module[ \t]*([a-zA-Z_0-9]+)/\1/m,module/
--regex-systemverilog=/^[ \t]*program[ \t]*([a-zA-Z_0-9]+)/\1/p,program/
--regex-systemverilog=/^[ \t]*interface[ \t]*([a-zA-Z_0-9]+)/\1/i,interface/
--regex-systemverilog=/^[ \t]*typedef[ \t]+.*[ \t]+([a-zA-Z_0-9]+)[ \t]*;/\1/e,typedef/
--regex-systemverilog=/^[ \t]*`define[ \t]*([a-zA-Z_0-9]+)/`\1/d,define/

--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*shortint[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*int[ \t]*(unsigned)?[ \t]*([a-zA-Z_0-9]+).*/`\6/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*longint[ \t]*(unsigned)?[ \t]*([a-zA-Z_0-9]+).*/`\6/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*byte[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*bit[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*logic[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*reg[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*integer[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*(rand)?[ \t]*time[ \t]*([a-zA-Z_0-9]+).*/`\5/v,variable/

--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*real[ \t]*([a-zA-Z_0-9]+).*/`\4/v,variable
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*shortreal[ \t]*([a-zA-Z_0-9]+).*/`\4/v,variable/

--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*chandle[ \t]*([a-zA-Z_0-9]+).*/`\4/v,variable/
--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*string[ \t]*([a-zA-Z_0-9]+).*/`\4/v,variable/

--regex-systemverilog=/^[ \t]*(static)?[ \t]*(local)?[ \t]*(private)?[ \t]*event[ \t]*([a-zA-Z_0-9]+).*/`\4/v,variable/

--regex-systemverilog=/^[ \t]*`SVT_REPLACEABLE_DEFINE\([ \t]*([a-zA-Z_0-9]+),.*\)/`\1/d,define/

--systemverilog-kinds=+ctfmpied

--langdef=altsystemverilog
--regex-altsystemverilog=/^[ \t]*(extern)?[ \t]*(virtual)?[ \t]*(protected)?[ \t]*class[ \t]*([a-zA-Z_0-9]+)/\4/c,class/
--regex-altsystemverilog=/^[ \t]*(extern)?[ \t]*(virtual)?[ \t]*(protected)?[ \t]*task[ \t]*.*[ \t]+([a-zA-Z_0-9]+)[\t]*[(;]/\4/t,task
--regex-altsystemverilog=/^[ \t]*(extern)?[ \t]*(virtual)?[ \t]*(protected)?[ \t]*function[ \t]*.*[ \t]+([a-zA-Z_0-9]+)[ \t]*[(;]/\4/f,function/
--regex-altsystemverilog=/^[ \t]*(virtual)?[ \t]*task[ \t]*.*[ \t]+([a-zA-Z_0-9]+)[\t]*[(;]/\2/t,task/
--regex-altsystemverilog=/^[ \t]*(virtual)?[ \t]*function[ \t]*.*[ \t]+([a-zA-Z_0-9]+)[ \t]*[(;]/\2/f,function/

Corresponding vim configuration

tags are separated by commas, and each tag ends with a semicolon. After each write, update tags

set tags=./.tags;,/home/synopsys/vcs/O-2018.09-SP2/etc/uvm-1.2/.tags;
autocmd BufWritePost * call system("ctags -R --extras=+q --fields=+i -n -f .tags")

Posted by njwan on Thu, 12 May 2022 18:48:45 +0300