fpga based serial port map transmission sdram cache vga display

brief introduction

On DE2 development board, use serial port to receive 640 * 480 color pictures sent by Qt program on PC, store them in SDRAM in RGB565 format, and display them on the screen through VGA.
Development board: DE2
Development tool: Quartus II 13.0 + Modelsim 10.5 SE
Global clock: 50M
VGA clock: 25M
SDRAM clock: 100M

overall structure

The figure above shows the overall structure of the system, omitting the PLL module. In fact, both FIFOs are inside the SDRAM controller.
There are five modules in total: PLL, serial port receiving, data merging, SDRAM controller and VGA controller

Module introduction

The PLL module is responsible for generating three clocks:

  • 25M clock: VGA
  • 100M clock: used by SDRAM controller
  • 100M(-90degree) clock: used by SDRAM chip

Serial port receiving module
Baud rate: 115200
Data bits: 8
Verification: None
Stop bit: 1

The serial port module is responsible for receiving the data sent by PC.
The serial port module is still used before and will not be modified. The interfaces are as follows:

module uart_rx(
    input               clk,
    input               rst_n,
    // uart rx
    input               rx,
    // output data & valid
    output reg          valid,
    output reg [7:0]    data

Data merging module
Because the RGB565 format is used to store color pictures, the single byte data received by the serial port should be combined into 16 bit wide RGB565 format data. The interfaces are as follows:

module data_merge(
    input               clk,
    input               rst_n,
    // input data & valid
    input               iValid,
    input       [7:0]   iData,

    // output data & valid
    output reg          oValid,
    output reg  [15:0]  oData

sdram controller module
The SDRAM controller module is responsible for storing pictures. The SDRAM controller was written by the big brother crazybingo, but it is essentially improved according to the SDRAM controller provided by Youjing. I want to stand on the shoulders of giants. The interfaces are as follows:

module Sdram_Control_2Port(
	//	HOST Side
	input                           REF_CLK;                //sdram control clock
	input                           OUT_CLK;                //sdram output clock
	input                           RESET_N;                //System Reset
	//	FIFO Write Side 1
	input   [`DSIZE-1:0]            WR_DATA;                //Data input
	input							WR;						//Write Request
	input	[`ASIZE-1:0]			WR_MIN_ADDR;				//Write start address
	input	[`ASIZE-1:0]			WR_MAX_ADDR;			//Write max address
	input	[8:0]					WR_LENGTH;				//Write length
	input							WR_LOAD;				//Write register load & fifo clear
	input							WR_CLK;					//Write fifo clock
	//	FIFO Read Side 1
	output  [`DSIZE-1:0]            RD_DATA;                //Data output
	input							RD;						//Read Request
	input	[`ASIZE-1:0]			RD_MIN_ADDR;				//Read start address
	input	[`ASIZE-1:0]			RD_MAX_ADDR;			//Read max address
	input	[8:0]					RD_LENGTH;				//Read length
	input							RD_LOAD;				//Read register load & fifo clear
	input							RD_CLK;					//Read fifo clock
	//STATUS Side
	output							busy;
	//	SDRAM Side
	output  [`ROWSIZE-1:0]          SA;                     //SDRAM address output
	output  [1:0]                   BA;                     //SDRAM bank address
	output  	                    CS_N;                   //SDRAM Chip Selects
	output                          CKE;                    //SDRAM clock enable
	output                          RAS_N;                  //SDRAM Row address Strobe
	output                          CAS_N;                  //SDRAM Column address Strobe
	output                          WE_N;                   //SDRAM write enable
	inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
	output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
	output							SDR_CLK;				//SDRAM clock

VGA controller module
VGA controller is responsible for generating VGA timing and driving the display screen.
Use the VGA controller in Youjing data disk. The interfaces are as follows:

module	VGA_Ctrl	(
	//	Host Side
	input		[7:0]	iRed;
	input		[7:0]	iGreen;
	input		[7:0]	iBlue;
	output		[20:0]	oAddress;
	output		[10:0]	oCurrent_X;
	output		[10:0]	oCurrent_Y;
	output				oRequest;
	//	VGA Side
	output		[7:0]	oVGA_R;
	output		[7:0]	oVGA_G;
	output		[7:0]	oVGA_B;
	output	reg			oVGA_HS;
	output	reg			oVGA_VS;
	output				oVGA_SYNC;
	output				oVGA_BLANK;
	output				oVGA_CLOCK;
	//	Control Signal
	input				iCLK;
	input				iRST_N;	

The top-level modules can instantiate the above modules.

Qt upper computer program

After studying Qt for a period of time, I finally wrote this serial port image transmission program, with more than 100 lines of code. You can choose any 640 * 480 resolution color picture, and RGB888 will be converted to RGB565 in the program. Although the interface is a little ugly, it is made step by step, and there is still a sense of achievement. As shown in the figure:

Effect demonstration

Link: https://www.bilibili.com/video/BV1YY4y147KC

fpga serial port transmission diagram

Tags: Cache FPGA sdram

Posted by chopper_pc on Fri, 13 May 2022 04:35:13 +0300